Program instructions generally comprise one to three bytes. The first byte is known as the opcode; it specifies the operation to be performed. Instruction bytes following the opcode, if any, may be data or address bytes (or both).
An instruction is first fetched and then executed. In the fetch phase, the instruction is fetched from microprocessor memory and transferred to the microprocessor control unit (CU). The CU is implemented, for example, by microprogramming a programmable logic array (PLA). The CU sequences the operation of the entire microprocessor. It generates synchronization signals and manages the commands exchanged between the microprocessor unit (MPU), input/output device (I/O) and memory.
The CU must perform a memory fetch for each instruction byte. The CU is generally programmed to "know" the number of bytes in each instruction; that is, the CU knows whether to go back to memory to fetch additional bytes after fetching the first byte or opcode.
A program instruction requires one or more machine cycles to execute. In the 6500 family of microprocessors, a machine cycle corresponds to the period of a microprocessor clock (.phi..sub.2), and a typical instruction can be executed in 1-7 machine cycles. The last machine cycle of any instruction includes the opcode fetch for the next instruction. During the opcode fetch, the appropriate program instruction is read from memory, and the instruction is gated over the data bus to the CU. Appropriate signals, including a SYNC pulse, are generated by the CU to execute a fetched instruction during the second half of a machine cycle. In the 6500 family of microprocessors, SYNC pulses cannot be generated every machine cycle due to the PLA characteristics. Thus, the SYNC pulse can at best be generated every other machine cycle. As a result, an instruction following a single byte instruction, i.e., an instruction which takes only one machine cycle to execute (referred to hereafter as a "single cycle" instruction), effectively occupies two machine cycles so that the next fetched instruction waits an extra machine cycle before it can be executed.
The present invention is directed to a technique for speeding up execution of program instructions, wherein at least one instruction can be executed in a single machine cycle, so that execution of the instruction following the single cycle instruction will begin in the very next machine cycle.